1. Field of the Invention
The present invention relates to a bidirectional bus system capable of bidirectional communication between two or more equipments, and more particularly, to a bidirectional level shift circuit used in a bidirectional bus system such as an I2C bus.
2. Description of the Related Art
The I2C bus developed by Phillips Corporation is used in a system for controlling various kinds of LSI (large-scale integration circuit). Recently, a HDMI (High Definition Multimedia Interface) standard connecting a digital television and a DVD (digital versatile disk) equipment by a high-speed digital base band communication has been developed as HDMI version 1.3 specification. According to the HDMI standard, the I2C bus operating with a power supply voltage of 5V is used for a DDC (Display Data Channel) that is a signal line for communicating display information between a transmitting side and a receiving side, and a signal line of a differential current mode operating with a power supply voltage of 3.3V is used for a TMDS (Transition Minimized Differential Signaling) line for communicating a high-speed image and audio digital data.
Therefore, equipment having a HDMI interface is mostly equipped with both an LSI operated with a power supply of 3.3V and an LSI operated with a power supply of 5V, and in many cases, a bidirectional level shift circuit is needed for converting a DDC signal for 3.3V outputted from a control microcomputer and the like to a DDC signal for 5V based on the HDMI standard. Thus, a level shift circuit for use in the I2C bus disclosed in the I2C Bus Specification Version 2.1 developed by Phillips Corporation or disclosed in the Japanese Translation Publication No. 2004-506979 is used for connecting the I2C bus for 3.3V system and the I2C bus for 5V system.
Here, an operation of a bidirectional level shift circuit defined in the I2C bus specification version 2.1 is described with reference to FIG. 6. In the bidirectional level shift circuit shown in FIG. 6, an I2C bus 611 (comprised of a serial data line SDA1 and a serial clock line SCL1) operating at a power supply voltage VDD1 of 3.3V is connected to an I2C bus 612 (comprised of a serial data line SDA2 and a serial clock line SCL2) operating at a power supply voltage VDD2 of 5V through a pair of N-type MOS transistors 68 contained in a semiconductor device 69. Each gate terminal of the pair of N-type MOS transistors 68 is connected to the power supply VDD1 of 3.3V. In addition, the I2C bus signal lines 611 on the 3.3V side and the I2C bus signal lines 612 on the 5V side are respectively connected to the 3.3V power supply VDD1 and the 5V power supply VDD2 through pull-up resistors Rp1 and Rp2. Here, reference numeral 61 denotes a first power supply terminal which receives the first voltage level, 62 designates a first signal terminal operating at the first voltage level, and 64 designates a second signal terminal operating at the second voltage level.
The operation in the case of communication directed from the I2C bus 611 on the 3.3V side to the I2C bus 612 on the 5V side is firstly described. When a signal on the 3.3V side is at a level of 3.3V that is a logic value of H (high) level, a gate-source voltage VGS of each N-type MOS transistor 68 is less than a threshold voltage thereof and the N-type MOS transistor is in OFF state. Therefore, the signal on the 5V side becomes a level of 5V that is a logic value of H level through the pull-up resistors Rp2. On the contrary, when the signal on the 3.3V side is at a level of 0V that is a logic value of L (low) level, a voltage more than the threshold voltage is applied as the gate-source voltage VGS of the N-type MOS transistor 68, so that the N-type MOS transistor 68 becomes ON state. Thus, the signal on the 5V side can be lowered to L level.
Next, the operation in the case of communication directed from the I2C bus 612 on the 5V side to the I2C bus 611 on the 3.3V side will be described. When a signal on the 5V side is at a level of 5V that is a logic value of H (high) level, a gate-source voltage VGS of each N-type MOS transistor 68 is less than the threshold voltage thereof and the N-type MOS transistor 68 is in OFF state. Therefore, the signal on the 3.3V side becomes a level of 3.3V that is a logic value of H level through the pull-up resistors Rp1. On the contrary, when the signal on the 5V side is at a level of 0V that is a logic value of L (low) level, a voltage more than the threshold voltage is applied as the gate-source voltage VGS of the N-type MOS transistor 68, so that the transistor 68 becomes ON state. Thus, the signal on the 3.3V side can be lowered to L level.
Thus, according to the bidirectional level shift circuit described in the I2C bus specification version 2.1 shown in FIG. 6, the I2C bus on the 3.3V side and the I2C bus on the 5V side are connected by a wired AND so that the bidirectional communication can be implemented between the above two I2C buses. In addition, this circuit configuration has an advantage such that, in the case where the power supply VDD1 on the 3.3V side and the power supply VDD2 on the 5V side are applied at the same time, only a voltage less than a voltage difference between the two power supply voltages is applied to the gate-source VGS and the gate-drain VGD of each N-type MOS transistor 68. Therefore, a withstand voltage between the gate and source and between the gate and drain of the N-type MOS transistor 68 can be lowered. Thus, even the level shift circuit between 3.3V and 5V can be configured by an N-type MOS transistor having a withstand voltage of 3.3V between the gate and source and between the gate and drain.
However, in the conventional bidirectional level shift circuit described in the I2C bus specification version 2.1 shown in FIG. 6, there is a problem that, in the case where the power supply VDD1 on the 3.3V side drops to 0V while the power supply on the 5V side is continuously applied, the VGD of 5V is applied between the gate and drain of the N-type MOS transistor 68. Therefore, in the conventional bidirectional level shift circuit shown in FIG. 6, it is necessary to use an N-type MOS transistor with a gate oxide film having a withstand voltage of 5V or more between the gate and source and between the gate and drain under the usage condition that the power supply on the 3.3V side drops to 0V while the power supply on the 5V side is being applied.
Meanwhile, since a process for a high-speed operation at an order of GHz such as TMDS signal of HDMI uses a very fine CMOS having a gate length of less than 110 to 130 nm, or a high-frequency Bi-CMOS using a SiGe-HBT (Heterojunction Bipolar Transistor), it is very difficult to integrate a level shift circuit between a super-fast TMDS signal using a 3.3V power supply and a DDC signal using a 5V power supply in one semiconductor device.